摘要
设计了用于无绳电话的45/48 MHz 接收机锁相环频率合成器,电路采用0.35μm CMOS 工艺,整数分频方式,外接 LC 谐振回路来调节环路工作在34 MHz、37 MHz两个频段,每个频段包括20个信道,间隔25k为一个信道,本文用 SMIC 0.35μm CMOS 工艺参数对所设计的频率合成器进行了仿真,仿真结果表明:在电荷泵充放电电流为1mA 时,整体电路工作电流小于2.5mA,spur 小于—60dBc,锁定时间小于3ms。
A fully integrated 45/48 MHz PLL Frequency Synthesizer for cordless phone receiver was presented. It has two bands and each band has 20 channels of channel space 25 KHz. This PLL was simulated based on a 0.35μm n--well CMOS process. The simulation results show that its average operating current is less than 2.5 mA, spur is less than -60 dBc, locked time is less than 3 ms when the current of CP is 1 mA.
出处
《南开大学学报(自然科学版)》
CAS
CSCD
北大核心
2007年第1期109-112,共4页
Acta Scientiarum Naturalium Universitatis Nankaiensis