AES算法的一种具有成本效益的FPGA实现方法

A Cost-Efficient Implementation of AES Algorithm Based on FPGA

为增强通信过程的保密性,对数据进行加密是最可靠和可行的处理办法。高级加密标准(AES)具有高效、灵活等优点。提出了一种基于FPGA的AES实现方式,在设计中通过采用等效解密过程、合并查找表、复用操作函数等方法,对其实现过程做了优化。在Quartus II下的试验结果表明这种实现方式减少了对存储单元和可编程逻辑单元的耗费。节约了FPGA器件的成本,实现了信息的安全传输。

To enhance the secret of communication, cryptography is reliable and practicable. AES（Advanced Encryption Standard）has the merits of efficiency and flexibility. This paper describes the AES algorithm and optimizes its implementation through adopting the equivalent deciphering process, integrating LUT（Look-up Table） and reusing functions. The result under Quartus II indicates this implementation decreases the required memory and logic units, economizing FPGA cost and ensuring information security.