摘要
由于门阵列ＶＬＳＩ半定制的性质，使其电路设计在许多方面都有着与众不同的特点．本文就门阵列电路中门的扇入与扇出、缓冲单元的设计、门电路的可测性设计等几方面问题进行了较详尽的分析与论述，以期对ＣＭＯＳ门阵列的ＡＳＩＣ研制，在高层次的电路设计上探讨优化设计方法．
ecause of the semi-custom feature of Gate Array VISI,there exist many differences between the circuit design in gate array form and in other forms. This paper analyses and discusses problems on several aspects of gate array circuit design,such as fan-in/fan-out of the gate,buffering & buffer macro design,test design of gate array circuits,etc,The purpose of this paper is to research for optimization design methodology of CMOS gate array ASIC in a higher hierarchy.
