CRC码的FPGA实现

Implementation of CRC Based on FPGA

介绍了循环冗余校验CRC算法原理和校验规则,分析了CRC校验码的具体计算过程,并以CRC-16为例,给出了使用硬件描述语言Verilog HDL来实现CRC-16的部分源程序,它既是校验码的生成器,也是待校验数据的校验器,对该例进行仿真并给出综合结果,最终可以在现场可编程门阵列(FPGA)上实现,其工作频率可达400 MHz.

This paper introduces the algorithm, theory and checking regulations of CRC, analyzes the computational process of CRC, takes CRC-16 as an example and gives some of the source program of hardware description language Verilog HDL to achieve CRC-16. It is not only the generator of check codes but also the parity checker of data waiting for checking. This paper gives the result of emulation and synthesis of the example, which can be realized in field programmable gate array （FPGA） with a work frequency up to 400 MHz.