高栅压下超薄栅nMOSFET的RTS噪声

RTS Noise in Ultra-Thin Oxide nMOSFET under High Gate Bias

在深入研究SMIC90nm工艺1.4nm栅厚度nMOS器件RTS噪声时域特性的基础上,提出了该类噪声电子隧穿栅介质的物理起源,并对高栅压下RTS噪声机理作了深入阐述.结合IMEC和TSMC的研究,建立了栅压与RTS噪声时间参数的物理模型,实验结果和模型模拟结果的一致说明了模型的有效性.该研究为边界陷阱动力学和此类器件可靠性提供了新的研究手段.

The timing characteristics of RTS in SMIC 90nm CMOS nMOS devices with a 1.4nm gate oxide are measured and analyzed. It is proposed that tunneling through the gate dielectric of electrons in the conduction band is responsible for RTS noise,and a detailed description of the mechanics of the RTS noise under high gate bias is presented. Also, based on the research from IMEC and TSMC,a physical model of the timing characteristics of the RTS noise versus gate bias is constructed, and the consistency of the experiment and the simulation shows the effectiveness of this model. The research in this paper provides new measures for dynamic characterization of border traps and the reliability of deep sub-micron MOS devices.