摘要
在讨论内进化演化硬件运行机制的基础上，详细介绍了基于虚拟可重构电路（VRC）的演化硬件平台的实现方法及演化平台的组成，描述了可重配置功能块（CFB）组成的阵列及CFB之间通过多路选择开关电路建立信号传输通道。在此基础上进行了1位全加器的演化，证明了这种方法的有效性。
Based on the operating mechanism of intrinsic evolvable hardware （ EHW）, a relative platform implemented with virtual recofigurable circuits （VRC） is discussed. This platform is composed of population memory, fitness evaluation circuits, crossover and mutation circuits, and evolvable object circuits. VRC is an array of Configurable Functional Blocks （CFB）. By using the multiplexers, the routings of the circuits in CFB can be created effectively. Based on this platform, we have designed and implemented an experiment of 1 bit adder, and proved the validity of the method.
出处
《军械工程学院学报》
2007年第1期66-68,共3页
Journal of Ordnance Engineering College
基金
国家自然科学基金资助项目（60471022）
关键词
演化硬件
FPGA
虚拟可重构电路
可重配置功能块
evolvable hardware
FPGA
virtual reconfigurable circuits
configurable functional blocks
