摘要
介绍了一种用数字锁相环对QPSK信号解调的方法,并将该算法在FPGA硬件中实现,给出了硬件实现FPGA的解调效果及解调的性能指标。通过解调算法和原理上的分析对QPSK信号解调全过程进行了详细说明。
A novel design method of the FPGA implementation of QPSK demodulation is proposed. The principal of the algorithms of QPSK demodulation via digital phased lock loop (PLL) approach is thoroughly analyzed. The effectiveness of the FPGA hardware realization of QPSK signal demodulation is proved and performance of the method is given.
出处
《通信对抗》
2007年第1期54-58,共5页
Communication Countermeasures
关键词
COSTAS
锁相环
载波同步
相位误差
COSTAS Loop
phase lock loop (PLL)
carrier frequency synchronization
phase error