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X86结构中微程序ROM的实现技术浅析 被引量:1

The Realization of Micro-programming ROM in X86 Micro Architecture
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摘要 微程序控制是X86结构的一个显著特点,深入剖析了X86结构中微程序部件的结构形式,对微程序ROM的结构组织、具体电路的实现形式等问题进行了较为详尽的阐述。 In today's CPU technology field, X86 processors and its ramifications hold a huge quotient in market of desktop computers. The research on X86CPU is still very important. And in most of modem CISC processors, microprogramming is the biggest prominence. For this reason, this article provides the deconstruction of micro program part in X86 architecture, especially to the ROM organization, circuit realization and etc.
出处 《微电子学与计算机》 CSCD 北大核心 2007年第4期37-41,共5页 Microelectronics & Computer
基金 国家自然科学基金项目(60573173)
关键词 复杂指令集计算机 X86结构 ROM组织 电路实现 CISC X86 architecture ROM organization circuit realization
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  • 1I Hamzaoglu,J Patel.Reducing Test Application Time for Built-in Self-test Pattern Generators,in Proc.VLSI Test Symp.,2000:369~376
  • 2Reducing test Application Time for Full Scan Embedded Cores.in Proc.Int.Symp.Fault Tolerant Comput.,1999:260~267
  • 3S Hellebrand,J Rajski,S Tarnick,S Venkataraman,et al.Built-in test for Circuits with Scan Based on Reseeding of Multiple-polynomial Linear Feedback Shift Registers.IEEE Trans.Comput.,Feb.1995,44:223~233,
  • 4C Barnhart,V Brunkhorst,F Distler,et al.Extending OPMISRbeyond 10_ scan Test Efficiency.IEEE Design Test Comput.,Sept./Oct.2002,19:65~73
  • 5R Dorsch,H-J Wunderlich.Tailoring ATPG for Embeddedtesting.in Proc.ITC,2001:530~537
  • 6P T Gonciari,B M Al-Hashimi,et al.Variable Length input Huffman Coding for System-on-a-chip Test.IEEE Trans.Computer-Aided Design,June 2003,22:783~796
  • 7Reto Zimmermann,et al.Low-Power Logic Styles:CMOS Versus Pass-Transistor Logic[J].IEEE Journal of Solid-State Circuits,1997,32(7):1079~1090
  • 8J M Quintana,et al.Low-power Logic Styles for Fulladder Circuits[A].Electronics,Circuits and Systems,The 8th IEEE International Conference on[C].Malta,2001:1417~1420
  • 9Chip-Hong Chang,et al.A Novel Low Power Low Voltage Full Adder Cell[A].Image and Signal Processing and Analysis,Proceedings of the 3rd International Symposium on[C].Rome,Italy,2003:454~458
  • 10Jan M Rabaey,et al.Digital Integrated Circuits:a Design Perspective (2nd Ed.)[M].New Jersey,USA:Prentice hall,2003

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  • 1胡伟武,张福新,李祖松.龙芯2号处理器设计和性能分析[J].计算机研究与发展,2006,43(6):959-966. 被引量:37
  • 2Huang Yongqin,Yuan Aidong,Li Jun. A Novel Directory-Based Non-busy, Non-blocking Cache Co- herenee[A].Wuxi:IEEE,2010.21-24.
  • 3Brown J A,Porter L,Tullsen D M. Fast thread mi-gration via cache working set prediction[J].IEEE High Performance Computer Architecture,2011,(02):31-34.
  • 4Teng-Feng Yang,Chung-Hsiang Lin,Chia-Lin Yang. Cache-aware task scheduling on multi-core architecture[J].VLSI Design Automation and Test,2010.
  • 5Dhakad P,Katariya A,Arya A. Performance Verifi- cation for Cache Memory of Multieore Processor[J].IEEE Computational Intelligence and Communication Networks,2011,(05):43-45.
  • 6Pease R L,Sternberg A L,Boulghassoul Y. Comparison of SETs in bipolar linear circuits generated with an ion microbeam, laser light, and circuit simula- tion[J].IEEE Transactions,.
  • 7陈鹏,袁雅婧,桑红石,张天序.一种可扩展的并行处理器模型设计及性能评估[J].航空兵器,2011,18(5):56-61. 被引量:6
  • 8何荣森,何希顺,张跃.从ARM体系看嵌入式处理器的发展[J].微电子学与计算机,2002,19(5):42-45. 被引量:16

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