摘要
The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.
设计实现了一种应用于IEEE802．11a收发信机的PLL频率综合器中的可编程分频器．介绍了逻辑综合、版图规划、布局布线等VLSI设计流程的关键步骤，通过将后端信息返标到前端设计工具，生成自定义线负载模型，优化了深亚微米工艺下的设计流程．可编程分频器采用Artisan TSMC0．18μm CMOS标准单元库设计并流片．芯片内核面积为1360．5μm^2，可工作在100～200MHz的频率范围．测试结果表明芯片能够完成精确的分频比．
基金
The National Natural Science Foundation of China(No60472057)
