11.6-GHz 0.18-μm monolithic CMOS phase-locked loop

11.6-GHz 0.18-μm CMOS锁相环电路(英文)

A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.

利用截止频率为49GHz的0.18-μm CMOS工艺,设计实现了11.6-GHz锁相环电路.该电路由模拟乘法鉴相器、单极点低通滤波器及采用可变负电阻负载的三级环形振荡器构成.在片晶圆测试表明,该芯片在输入速率为11.6GHz、长度为231-1伪随机序列的情况下,恢复时钟的均方根抖动为2.2ps.锁相环的跟踪范围为250MHz.环形振荡器在偏离中心频率为10MHz处的单边带相位噪声为-107dBc/Hz.在锁定条件下,锁相环在偏离中心频率为10MHz处的单边带相位噪声为-99dBc/Hz.芯片面积为0.47mm×0.72mm,在1.8-V电源供电下,功耗为164mW.