用于混合信号集成电路的低噪声电流型触发器

Novel low-noise current-mode flip-flops for mixed-signal integrated circuits

提出了一种以电流信号表示逻辑值的低噪声触发器设计方案,用于在混合集成电路的设计中取代传统的CMOS触发器,以减少存贮单元开关噪声对模拟电路性能的影响.所设计的结构包括主从型单边沿触发器、单闩锁单边沿触发器和单闩锁双边沿触发器.单闩锁结构的触发器不仅可以简化电路结构,更为重要的是它大大降低了电流型触发器的直流功耗.在保持相同数据吞吐量的条件下,应用单闩锁双边沿触发器可以使时钟信号的频率减半,从而进一步降低时钟网络的动态功耗.采用0.25μm CMOS工艺参数的HSPICE模拟结果表明,所提出的电流型触发器工作时,在电源端产生的电流波动远远小于传统的CMOS电路.

A new low-noise implementation of edge triggered flip-flop was presented to replace the conventional CMOS flip-flop in mixed-mode integrated circuits （ICs） to reduce the impact of digital switching noise on the performance of analog circuits. The logic levels of the proposed flip-flop were realized in the current domain by steering a constant direct current （DC） bias current. Three configurations including master-slave single edged-triggered （MS-SET） flip-flop, one-latch single edged-triggered （1L-SET） flip-flop and one-latch double edged-triggered （1L-DET） flip-flop were deigned. In one-latch single edge-triggered and double edge-triggered configurations, data are sampled into the latch during a short transparency period for one edge and each edge of the clock signal respectively. Compared with master-slave flip-flop, the one-latch configurations have less transistor counts and lower static power consumption. For a given throughput, the clock frequency can be halved using double edged-triggered flip-flops. Therefore the dynamic power dissipation of the clock network can be reduced. HSPICE simulations using 0.25 μm CMOS technology showed that the current spikes due to switching are much reduced in the proposed flip-flops compared with conventional CMOS circuits. The reduction in digital switching noise allows the development of higher performance on-chip analog circuitry in CMOS mixed-mode applications.