分数像素运动矢量代价产生器的VLSI设计

Analysis and VLSI Design for Reusable Fractional Motion Vector Cost Generator

针对H.264/AVC视频编码器的系统芯片设计,通过分析分数像素运动估计(FME)模块的数据并行度和硬件利用率,探讨了分数像素运动矢量代价产生器的复用结构,再依据FME模块的具体设计约束,提出了可以复用产生1/2像素和1/4像素运动矢量代价的硬件实现结构,并且在FPGA开发板上进行了分数像素运动矢量代价产生器的设计验证。

In the VLSI design of H.264/AVC encoder chip,based on data parallelism and hardware utilization of fractional motion estimation （FME） module, the possibility of reusable VLSI architecture for fractional pixel motion vector cost generator is analyzed. And then, according to these actual constraints of FME module,we propose a reusable VLSI architecture for 1/2 and 1/ 4 pixel motion vector generator. Moreover,these designs are implemented on FPGA development board .