非规则LDPC码译码改进算法及其DSP实现

Improved decoding algorithm for irregular low-density parity-check codes and its implementation with DSP

为了降低非规则低密度奇偶校验(low-density parity-check,LDPC)码译码算法的复杂度,提出一种适合数字信号处理器(digital signal processor,DSP)实现的低运算复杂度、低误码平台译码的改进算法。该算法校验节点的运算采用修正最小和算法,外信息的更新采用串行方式,既保持了串行和积算法在有限迭代次数下译码门限低的优点,又降低了节点运算复杂度和误码平台。用定点DSP芯片实现的非规则LDPC码译码器的实测结果表明,该算法能以较低的实现复杂度获得低的误码平台和译码门限。

An improved decoding algorithm ,which aims to reduce the decoding complexity of irregular low-density parity-check （LDPC） codes, is presented for implementation with digital signal processors （DSPs） with reduced computation complexity and low error floor. The algorithm uses the modified min-sum （MMS） algorithm for check node processing with the extrinsic information updated sequentially, so that it exhibits a low decoding threshold with a limited number of iterations, while reducing the node processing complexity and error floor. Tests with a fixed-point DSP show that the algorithm achieves a low error floor and low decoding threshold with low implementation complexity.