FFT处理器的算术测试与可测性设计

Arithmetic test and design-for-testability for FFT processor

针对快速傅里叶变换处理器,本文提出了一种有效的可测性设计及其测试方案。测试时,该方案将处理器中的寄存器作为扫描链提高了其可控性,利用其中的加法器作为测试生成,生成的测试矢量能侦测处理器每个基本组成单元内部的任意组合失效。由于处理器中一些加法器、寄存器的再利用,以及电路结构的规则性,因而只需最少的额外硬件、面积开销即可真速、并行地实施该测试方案而不会降低电路性能。

This paper presents an effective design-for-testability and test scheme for （FFT） processor. During test, some registers in the processor are converted into scan chains to improve controllability of the circuit, the adders in the processor are used as test generators, and the produced test patterns can detect any combinational faults within every basic building cell of FFT processor. Because of the reuse of some building blocks, such as adders and registers in FFT processor, and the regularity of the circuit structure, the test scheme can be implemented at-speed and in parallel without circuit performance degradation, and with minimal additional hardware and area overhead.