快速实现基于FPGA的脉动FIR滤波器

Fast Implementation of the Systolic FIR Filter Based on FPGA

基于FPGA(现场可编程门阵列)器件内部集成的数字信号处理模块,利用QuartusⅡ中宏功能模块定制4阶卷积运算单元,利用VHDL(甚高速集成电路硬件描述语言)元件例化语句生成脉动阵列结构FIR(有限冲击响应)滤波器。研究了并利用PE(处理单元)结构时序约束和加法树结构的加法阵列优化设计性能。与已有的实现方法相比,文中提出的方法具有更短的设计周期、更强的可移植性、更高的工作频率和实时处理信号的能力。

Based on the integrated digital signal processing modules in FPGA, MegaWizard Plug-In Manager to customize 4 step convolution arithmetical processing elements in QuartusII is used, and a novel structure of systolic array for FIR filter with VHDL is proposed. The timing requirements for PE structure and the adder array for adder tree structure to optimize performance of design are studied and used. Through comparison with the other realization methods, the approach proposed in this paper has shorter design cycle, a stronger transplantibility, higher operating frequency and real-time signal processing ability.