高性能数字电视QAM初始解调器的VLSI结构设计

Design of a VLSI architecture for a high performance QAM initial demodulator for HDTV receiver

本文设计了一种适用于高清晰数字电视(HDTV)接收芯片的全数字正交幅度(QAM)解调器结构。该解调器由数字混频器、数字频率合成器(DDFS)和低通滤波器构成。提出采用最佳平方逼近算法优化DDFS的输出正余弦波形,使得最差情况下的无杂散动态范围(SFDR)小于-75dBc。同时,对低通滤波器的实现方式采用了正交信号复用和系数扩展的方法,优化了滤波器结构,降低了所需电路的面积。

An all-digital QAM initial demodulator architecture is presented for I-IDTV receiver chip. This initial demodulator incorporates a digital mixer, DDFS and low-pass filter. This paper presents a direct digital frequency synthesizer （DDFS） based on Least Square （LS） approximation to optimize sine-cosine wave to make SFDR in worst situation less than -75dBc. At the same time, by applying methods of complex quadrature signal and expand filter＇s coefficients, it optimizes the architecture of low-pass filter and reduces the area of circuit.