基于SOVA算法的Turbo译码器的设计与优化

Design and Optimization of Turbo Decoder Based on SOVA Algorithm

给出了基于SOVA算法的Turbo译码器的硬件设计系统结构,通过对关键模块的硬件资源占有及译码时序的分析,提出了减少硬件资源、降低硬件功耗以及提高译码速度、减少译码时延的优化设计方案。采用NC Simulator的仿真分析以及Cyclone II系列FPGA芯片的硬件测试表明,该文提出的优化设计方案减少了约40%的硬件资源,且译码速度提高了约60%,达到了降低功耗和提高速度的双重功效。

The system framework of hardware design for Turbo decoder based on SOVA algorithm is introduced. Through the analysis on the hardware resource occupancy and decoding delay of key modules, the optimization scheme which can decrease hardware resource, reduce power dissipation, improve decoding speed and reduce decoding delay is proposed. The simulation analysis with NC Simulator and hardware test with FPGA chip of Cyclone Ⅱshow that the proposed optimization method reduces about 40% hardware resource and improves 60% decoding speed. It achieves the double efficacy of reducing power dissipation and improving speed.