低功耗的可重构数据Cache设计

Low power reconfigurable data cache design

在嵌入式处理器中,Cache功耗所占的比重越来越大。提出了一种可重构的低功耗数据Cache,能够利用程序运行过程中的空间和时间局部性以及高频数据值局部性来节省功耗。Mibench和Mediabench的仿真结果表明,对于多媒体应用为主的测试程序,采用基于高频值的可重构低功耗数据Cache与普通Cache相比,平均能量消耗降低34.45%,平均能量延迟乘积降低27.50%。

Caches compose larger and larger proportion in the power consumption ofembedded processors. Alow-powerreconfigurable data design based on locality and frequent value locality is investigated. Mibeneh and Mediabeneh simulation results indicate that, compared with the frequent-value reeonfigurable data cache and the normal data cache, the average energy consumption decreases 34.45 %, while the average energy delay production improves 27.50 %.