H．264中DCT／IDCT／Hadamard变换多时钟方式的FPGA实现

A Multi-clock Domain FPGA Implementation of DCT/IDCT/Hadamard in H. 264

DCT／IDCT／Hadamard变换被广泛应用于多种视频编码标准中，而H．264／MPEG-4AVC作为新一代的视频压缩标准，它具有在相同图像质量下比其他视频压缩标准拥有更高的压缩率的特性，因此对于H．264／MPEG-4AVC中的DCT／IDCT／Hadamard变换的研究就有着十分重要的意义。对于H．264／MPEG-4AVC中变换算法进行分析，并且提出一种可用的高效的硬件实现电路结构，此电路结构能够并行计算4输入像素数据。

DCT/IDCT/Hadamard transform coding has been widely used in video coding standards. Under the same picture quality, MPEG -4AVC/H. 264, as a new video coding standard, can realize a higher hit-rate reduction and improvement in coding performance. It is very important to study the DCT/IDCT/Hadamard in MPEG- 4AVC/H. 264. In this paper, a hardware architecture for accelerate DCT/IDCT/Hadamard transformation coding is presented. This architecture can calculate 4 inputs in parallel.