高速时序信号完整性及时钟端接问题研究

Integrality and clock terminal of high speed time sequence signal

本文介绍了时序设计中经常出现的信号完整性问题及其对时序预算的影响,介绍了高速系统中传输线的分类、特性及其阻抗的计算。根据ICS953401在PC主板上应用时所出现的不同信号问题,分析了反射、振铃的产生原因,并使用相应的端接来改善时钟信号完整性。

The paper introduced the signal integrality problem in the time sequence design, and it impacted on time sequence budget. And the classification, characteristic, impedance computation of transmission line in the high-speed system were introduced too. When ICS93401 was used on PC motherboard, there was a different signal problem, according to it, the producing reasons of reflection and ringing were given , and used the corresponding terminal to improve the clock signal integrality.