异步FIFO中存储单元的分析设计

Analysis and Design of Memory Cell of Asynchronous FIFO

从异步FIFO的一般结构入手,重点对异步FIFO中的双端口RAM存储器进行了分析,深入研究了存储单元的读写工作原理,以此得出各单元管子参数设计的尺寸要求以及管子单元比(CR),并根据0.35μm CMOS工艺设计出了1k×9bit的异步FIFO,其读取速度约为10ns。

In this paper the common structure of the asynchronous FIFO is firstly introduced and the dual - port RAM is emphasized. Meanwhile, the way of reading and writing of the memory cell is deeply analyzed. So, the design of parameters and CR of the memory cells are researched. Finally, asynchronous FIFO of 1 k × 9bit is designed by technical library of 0.35μm CMOS. The velocity of reading and writing is about 10ns.