期刊文献+

一种安全可靠性高的全新IP核保护方法 被引量:2

A New IP Protection Method with High Safety
下载PDF
导出
摘要 提出了一种基于3DES加(解)密双方认证系统的IP核保护方法,主要用于保护基于SRAMD工艺FPGA设计的IP核电路。在配置好的FPGA中,通过IP核外附加的内部保护电路和外部验证设备之间的互相通信认证,确认使用者的合法性,可有效防止IP核信息配置到FPGA过程中的非法盗取。详细介绍了这种新IP核保护方法的原理、结构和实现过程,并设计了一套基于此技术的简化双方认证系统。 A new IP protection method is described, which is a mutual authentication based on triple DES and is applicable for protection of security for SRAM FPGA bit streams. Legality of the IP core user is assured through the communication authentication between inner protection circuit outside IP core in FPGA and the external authentication device, which protects IP core information efficiently from detection and replication when it is downloaded into FPGA. The principle, architecture and implementation of the IP core protection system are demonstrated, and a simplified mutual authentication system using this new technology is designed.
出处 《微电子学》 CAS CSCD 北大核心 2007年第2期185-188,共4页 Microelectronics
基金 上海-应用材料研究与发展基金资助项目(0506)
关键词 IP核保护 3DES 双方认证系统 FPGA IP core protections 3DES Mutual authentications FPGA
  • 相关文献

参考文献10

  • 1沈鹏,高志强.集成电路IP安全机制[J].半导体技术,2002,27(1):22-25. 被引量:2
  • 2Gajski D D.IP-based design methodology[A].Proc 36th Des Autom Conf[C].New Orleans,LA,USA.1999,43.
  • 3束礼宝,宋克柱,王砚方.伪随机数发生器的FPGA实现与研究[J].电路与系统学报,2003,8(3):121-124. 被引量:62
  • 4Data Encryption Standard.Federal Information Processing Standard 46[S].1997.
  • 5Des Mode of Operation.Federal Information Processing Standard 81[S].1980.
  • 6McLoone,M,McCanny J V.High-performance FPGA implementation of DES using a novel method for implementing the key schedule[J].IEE Proc Circ,Dev and Syst,2003,150(5):373-378.
  • 7汪翼,沈海斌,何乐年,严晓浪.DES算法的高速流水线实现[J].微电子学与计算机,2003,20(8):158-160. 被引量:16
  • 8Verbauwhede I,Hoornaert F,Vandewalle J,et al.Security and Performance Optimization of a New DES Data Encryption Chip[J].IEEE J Sol Sta Circ,1988,23(3); 647-656.
  • 9Xilinx公司.Data book[Z].1998.7
  • 10Altera公司.Data Book[Z].1999.12

二级参考文献13

  • 1Shneier B(美)著 吴世忠等译.应用密码学:协议、算法与C源程序[M].北京:机械工业出版社,2000.1.
  • 2NBS FIPS PUB 46. Data Encryption Standard. National Bureau of Standards, U.S. Department of Commerce, Jan 1977.
  • 3C S Steele, J G Koller. A Fully Pipelined, 700MBytes/s DES Encryption Core. Proceedings of Ninth Great Lakes Symposium on VLSI, 1999.
  • 4A G Broscius, J M Smith. Exploiting Parallelism in Hardware Implementation of the DES. Advances in Cryptography- CRYPTO'92 Proceedings, 1992:367-376.
  • 5BergamaschiR A.Automating the design ofSOC UsingCores[].IEEE Design andTest ofComputers.2001
  • 6Kawarabayashi,Masamichi.System level design method-ology for system on a chip[].NEC Research andDevelopment.2000
  • 7HopesT.Hardware/software co-verification, anIP vendorsviewpoint.ComputerDesign:VLSI inComputers andProcessors,1998.ICCD ’98[].ProceedingsInternationalConference on.1998
  • 8ChapmanR,DurraniT S.IP Protection ofDSP AlgorithmsforSystem onChipImplementation[].IEEE transactionson signal processing.2000
  • 9NealeR.VLSI attack design productivity andIPshortcomings[].Electronic Engineering.1998
  • 10KahngA B et al.Watermarking techniques for intellec-tual property protection.DesignAutomationConference,1998[].Proceedings.1998

共引文献77

同被引文献8

引证文献2

二级引证文献6

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部