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一种采用0.5μm CMOS工艺的多通道SAR ADC 被引量：2

Design of a Multi-Channel SAR ADC Based on 0.5μm CMOS Process
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摘要 设计并实现了一个多通道12位逐次逼近(SAR)A/D转换器。转换器内部集成了多路复用器和并行到串行转换寄存器、复合型DAC等。整体电路采用Hspice进行仿真,转换速率为133 ksps,转换时间为7.5μs。通过低功耗设计,工作电流降低为2.48 mA。芯片基于0.5μmCMOS工艺完成版图设计,版图面积为2.4 mm×2.3 mm,流片测试满足设计指标。 A multi-channel 12-bit SAR A/D converter is designed and implemented. Multi-switch circuit and parallel-to-serial data register are integrated in the circuit to realize multi-channel and serial interface. A unique configuration of equal-valued polysilicon resistors and rationed capacitors is adopted for D/A converter. The circuit is simulated using Hspice based on 0. 5 μm CMOS process. With consideration of low-power design, the total operating current is decreased to 2. 48 rnA. The digital data serial output has a conversion rate of 133 ksps and conversion time of 7. 5μs. The chip occupies an area of 2. 4 mm× 2. 3 mm. Test results show that the design specification has been achieved.
作者 彭新芒 杨银堂 朱樟明
机构地区 西安电子科技大学微电子研究所
出处 《微电子学》 CAS CSCD 北大核心 2007年第2期217-220,共4页 Microelectronics
基金 国家自然科学基金资助项目(60476046) 教育部博士学科点基金资助项目(20050701015) 部委基金资助项目(51408010304DZ0140 51408010205DZ0164)
关键词 逐次逼近模数转换器 复合结构DAC CMOS工艺 Successive approximation A/D converter Composite DAC CMOS process
分类号 TN432 [电子电信—微电子学与固体电子学]
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参考文献6

  • 1Hadidi K,Tso V S,Temes G C.An 8-b 1.3-MHz successive-approximation A/D converter[J].IEEE J Sol Sta Circ,1990,25(3):880-885.
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同被引文献25

  • 1Promitzer Gilbert.12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MHz[J].IEEE Journal of Solid-State Circuits,2001,36(7):1138-1143.
  • 2Park Jaejin,Park Hojin,Kim Jaewhui,et al.A 1 mW 10-bit 500 kHz SAR A/D converter[C]//IEEE International Symposium on Circuits and Systems.Geneva,Switzerland,2000:581-584.
  • 3Kim Hoonki,Min Youngjae,Kim Yonghwan,et al.A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array[C]//IEEE International Conference on Electron Devices and Solid-State Circuits.Hong Kong,China,2008:1-4.
  • 4Craninckx Jan,Van der Plas Geert.A 65fJ/conversionstep 0-to-50 MHz 0-to-0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS[C]//IEEE International Solid-State Circuits Conference.San Francisco,USA,2007:246-247.
  • 5Tan Kuo Hwi Roy,Teo T H.A0.9 V 100 nW rail-to-rail SAP,ADC for biomedical applications[C]//International Symposium on Integrated Circuits.Singapore,2007:481-484.
  • 6Franco Maloberti.Data Converters[M].Dordrecht:Springer,2007.
  • 7Ginsburg B P,Chandrakasan A P.An energy-efficient charge recycling approach for a SAR converter with capacitive DAC[C]//IEEE International Symposium on Circuits and Systems.Kobe,Japan,2005:184-187.
  • 8Chang Youkuang,Wang Chaoshiun,Wang Chorngkuang.A 8-bit 500 Hz low power SAR ADC for biomedical applications[C]//IEEE Asian Solid-State Circuits Conference.Jeju,South Korea,2007:228-231.
  • 9Ginsburg B P,Chandrakasan A P.Dual time-interleaved successive approximation register adcs for an ultrawideband receiver[J].IEEE Journal of Solid-State Circuits,2007,42(2):247-257.
  • 10Verma Naveen,Chandrakasan A P.An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes[J].IEEE Journal of Solid-State Circuits,2007,42(6):1196-1205.

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二级引证文献6

微电子学
2007年 第2期

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