用于H.264的高性能整像素运动估计VLSI的设计

VLSI Design of High Performance Full-Search Block-Matching Full-Pel Motion Estimation Processor for H.264

给出了一种用于H.264变块尺寸全搜索块匹配算法的运动估计电路的改进结构,并完成了VLSI设计。通过脉动阵列和全流水线的设计,达到最高的数据重用率、最小的I/O引脚数和100%的硬件计算效率。采用HJTC 0.18μm 1P6M CMOS工艺,完成了运动估计芯片的VLSI实现,芯片面积为4 mm×4 mm,最高工作频率125 MHz。仿真表明,本设计能实时处理SHDTV(1920×1080,60 f/s)视频序列,满足H.264的应用需求。

An improved architecture for H. 264 fulbpel motion estimation using variable block size full-search block-matching algorithm is proposed in this paper. To obtain the highest data reuse efficiency and minimum I/O pin count while achieving 100% hardware efficiency, a systolic array and full pipeline architecture is adopted. The motion estimation processor is implemented using HJTC＇s 0. 18μm 1-poly 6-metal CMOS technology, which occupies a silicon area of 4 mm × 4 mm and operates at 125 MHz. Experimental results show that this circuit is capable of processing Supper HDTV video sequences （1920 × 1080,60 f/s） in real-time, and so it is applicable for H. 264.