摘要
给出了一个电源电压为1.8 V、功耗为0.9 mW的4.8 GHz二分频器。该分频器采用基于反转触发器(TFF)的电路结构,使用动态负载,输出I、Q两路正交信号。对设计的电路采用标准UMC 0.18μm CMOS工艺进行了仿真,结果表明,该分频器工作频率可达6.5 GHz。
A high speed toggle flip-flop (TFF) based frequency divider is presented, which outputs two channels of orthogonal signals, I and Q, with dynamic load. Simulation in standard UMC's 0. 18μm CMOS process shows that the frequency divider operates well in the frequency range from 2 GHz to 6.5 GHz, with a 1.8 V supply voltage and 0. 9 mW power consumption.
出处
《微电子学》
CAS
CSCD
北大核心
2007年第2期279-281,共3页
Microelectronics
基金
国家自然科学基金资助项目(60236020
60475018)
北京市科技计划资助项目(D0305003040111)
关键词
分频器
反转触发器
动态负载
正交信号
Frequency divider
Toggle flip-flop
Dynamic loading
Orthogonal signal