摘要
在本文中，我们提出了一种离散小波变换（DWT）及其逆变换（IDWT）的VLSI结构，这一结构利用DWT／IDWT的结构和数值特性大大降低了系统的实现规模，同时由于采用了并行流水线和平衡数据通道等技术，可以获得每个时钟两个数据的处理速度和五个时钟节拍的流水线时延．基于硬件描述语言VHDL的模拟和综合结果表明，采用1．5μmCMOS工艺时，电路的规模为5058单元面积，在最坏情况下，最高时钟频率约可达55MHz，数据处理速度达到110Mpoints／s．
A specific VLSI architecture for forward/inverse DWT is presented in this paper. It uses the properties of the structure and coefficients to reduce the circuit area. In addition, the balanced pipeline has been adopted which results in a high throughput at 2 outputs per clock and 5 clocks pipeline latency. This circuit is verified by the hardware description language (VHDL). The synthesis results show that the circuit contains 5058area, the speed of data processing can reach 110 M points/s when 1. 5μm CMOS process technology is used.
