10级流水线双精度浮点乘法器的设计

Design of 10 Pipeline Stages Multiplier for Double Precision Floating Point Data

提出了一种基于IEEE754标准的双精度浮点乘法器的流水线设计方法.该方法面向32 bit数据通路的数字信号处理器,每个64 bit双精度浮点操作数划分为2个32 bit数据,采用32 bit×32 bit无符号阵列乘法器实现有效数的相乘,并通过控制部分积与其选择信号在流水线中的同步传递,用1个66 bit加法器实现了4个部分积的相加.采用提出的舍入方法完成了有效数的舍入.整个双精度浮点乘法器的设计分为10级流水线.硬件仿真验证了该方法的正确性和有效性.

A new design method of pipelined multiplier for double precision floating point data based on IEEE754 standard was proposed. The method is faced for digital signal processor with 32 bit data path. Each 64 bit operand was divided into two 32 bit data and the multiplication of significand was accomplished by 32 bit × 32 bit unsigned array multipliers. By transferring partial products and their selection signals synchronously, only one 66 bit adder was used to add all four partial products. A method for rounding was also proposed. The whole operation was divided into 10 pipeline stages. The correctness and performance can be confirmed by simulation results.