基于指令行为的Cache可靠性评估研究

Research on Reliability Evaluation of Cache Based on Instruction Behavior

软错误由高能粒子撞击所产生,对处理器的可靠性产生很大的损害.随着处理器设计目标转向低功耗、高性能和低供电电压,软错误的发生日益频繁,处理器的可靠性研究也随之受到越来越多的关注.针对传统的基于注错仿真的可靠性评估方法效率低的缺陷,提出了一套系统的cache可靠性评估方法,以可靠性指标之一---体系结构易受损因子(architectural vulnerability factor,AVF))---为研究对象,一方面,基于指令行为分析应用程序运行过程中对最终结果不产生影响的指令,从而确定对cache的AVF产生作用的指令;另一方面,根据cache的存储类型、所采取的写策略,结合cache中数据/指令阵列和地址标识阵列的特点,对cache上的各种相邻操作组合对AVF的影响进行了研究,从而完成AVF评估所需的信息分析.实验部分对PISA体系结构指令cache中的指令阵列进行了AVF评估,说明了该方法的有效性.

Soft error arises from the strike of high-energy particle, and does great harm to the reliability of processor. Furthermore, with the change of design targets of processor to low power consumption, high performance, and the reduction of supplying voltage, the occurrence possibility of soft error arises greatly. As a result, research on reliability of processor receives much more attention than ever. Aiming at solving the problem of low efficiency of traditional evaluation methods, which mostly apply fault-injection methods, this paper presents a systematic evaluation method of the indispensable memory unit in processor, cache. It takes an evaluation attribute, architectural vulnerability factor as research object. On the one hand, this method analyzes instructions that have no impact on the final execution result of application program to get the instructions that affect AVF. On the other hand, according to memory type, writing policy, and features of data/instruction and address tag array of cache, it analyzes various combination of neighboring operations＇ effects on AVF, thus attaining the needed information in AVF evaluation process. In the experiment, architectural vulnerability factor evaluation of instruction array of cache in PISA architecture is performed. The experiment results demonstrate the validity of this method.