数字式继电器延时电路的设计

Design of the Digital Switch Delay Circuit

本文叙述了数字式延时继电器专用大规模集成电路的逻辑设计与功能实现.该电路通过不同的选通器将得到3种经过延时后的脉冲信号,并增加了二一十进制的转换,吸收了国外电路编程序的优点,使用起来非常方便.

In the paper logical designing and functional realizing of large scale Application Spe-cific Integrated Circuit (ASIC) are described. The circuit can obtain three delayed pulse signal by different selectors and has added binary-decimal conversion. Because we have absorbed advantages of abroad circuit-programmer, it is convenient to use.