摘要
A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the center of the data eye exactly at the rising edge of the data-sampling clock. A single channel DR circuit was fabricated in TSMC＇s standard 0. 18μm CMOS process. The chip area is 0. 46mm^2. With a 2^32 - 1 pseudorandom bit sequence （PRBS） input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps. The sensitivity of the single channel DR is less than 20mV with 10-12 BER.
设计了一个应用于SFI-5接口的2·5Gb/s/ch数据恢复电路.应用一个延迟锁相环,将数据的眼图中心调整为与参考时钟的上升沿对准,因而同步了并行恢复数据,并降低了误码率.采用TSMC标准的0·18μm CMOS工艺制作了一个单通道的2·5Gb/s/ch数据恢复电路,其面积为0·46mm2.输入231-1伪随机序列,恢复出2·5Gb/s数据的均方抖动为3·3ps.在误码率为10-12的条件下,电路的灵敏度小于20mV.
