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一种新型的低功耗SEU加固存储单元 被引量：5

A Novel Low Power SEU Hardened Storage Cell
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摘要 提出了一种新的SEU加固单元,该单元在保持Whitaker单元基本结构的基础上增加4个晶体管以消除电平退化.SPICE模拟结果表明该单元读写功能正确,静态电流较Whitaker单元下降了4个数量级,写入速度和其他单元相当.通过DESSIS和SPICE混合模拟表明,该单元在LET为94MeV/(mg·cm2)的Au离子撞击下没有发生翻转. A novel storage cell is proposed. Its structure is similar to Whitaker＇s cell, but four transistors are added to avoid voltage degradation. SPICE simulation results show that its static current drops dramatically compared with Whitaker＇s cell, and the write speed is equivalent to that of other cells. No upset occurs when Au ions with an LET of 94MeV/（mg· cm^2） impacts by DESSIS and SPICE mix simulation.
作者 刘必慰 陈书明 梁斌
机构地区 国防科学技术大学计算机学院
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第5期755-758,共4页 半导体学报（英文版）
关键词 单粒子翻转 设计加固 存储单元 SEU hardening by design storage cell
分类号 TN492 [电子电信—微电子学与固体电子学]
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参考文献9

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同被引文献27

  • 1朱冰莲,孔杰.高效复数流水线蝶形单元的FPGA实现[J].电子测量与仪器学报,2005,19(4):77-80. 被引量：4
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  • 3BLUM D R,DELGADO - FRIAS J G. Comparison of SET - resistant approaches for memory - based architectures[ C]. in Proc. 12th NASA Syrup. VLSI Design, Coeur ddene,2005.
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  • 5N1KOLIE B, OKLOBDZIJIA V G, STOJANOVIC V, et al. Leung. Improved sense amplifier based flip flop: Design and measurements [ J ]. IEEE J. Solid - State Circuits, 2000,35 (6) : 876 - 884.
  • 6K.Kyriakoulakos and D.Pnevmatikatos, "A novel SRAM- based FPGA architecture for efficient TMR. fault tolerance support,"in Field Programmable Logic and Applications,2009.FPL 2009.International Conference on,31 2009-sept,2009:193-198.
  • 7D.Suzuki,T.Endoh,and T.Hanyu,"TMR-logic-based LUT for quickly wake-up FPGA,"in Circuits and Systems,2008. MWSCAS 2008.51st Midwest Symposium on,Aug,2008:326-329.
  • 8Cornelius C,Grassert F,K(o)ppe S. Deep submicron technology:opportunity or dead end for dynamic circuit techniques[A].India:Bangalore,2007.330-338.
  • 9Naffziger S D,Colon-Bonet G,Fischer T. The implementation of the itanium 2 microprocessor[J].IEEE Journal of Solid-State Circuits,2002,(11):1448-1460.
  • 10Munteanu D,Autran J L. Modeling and simulation of single-event effects in digital devices and ics[J].IEEE Transactions NS,2008,(04):1854-1878.

引证文献5

二级引证文献3

Journal of Semiconductors
2007年 第5期

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