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低硬件成本的高性能Hash算法加速器VLSI设计 被引量：2

A High-performance and Low-cost VLSI Implementation of the SHA-1 Hash Function
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摘要 本文基于安全Hash算法(SHA-1),提出了一种结构优化的SHA-1硬件加速器.本设计通过改进数据通路,加快了运算单元的速度;同时,采用动态操作数生成的方法,节约了硬件资源.设计采用SMIC0.25μm CMOS工艺综合,其核心电路(core)等效门为16.8k;在86MHz的工作频率下,其数据吞吐率达1.07Gbps.分析结果显示,该硬件加速器具备低成本和高性能的特点,适用于PDA、智能手机等面积受限的移动设备,具有良好的应用前景. This paper presents an optimized architecture of a SHA-1 accelerator, based on Security Hash Algorithm. By improving the datapath and adopting the dynamic operand generation technology, the proposed design achieves the goal of high-performance and low-cost. Based on SMIC 0. 25μm standard CMOS technology, the core circuit of this SHA-1 accelerator has about 16.8k gates. Under 86MHz system clock frequency, it achieves a throughput of about 1.07Gbps. The results shows that it is suitable for applications in PDA, mobile telephone, etc. , which demands limited area.
作者 顾叶华 曾晓洋 韩军 张章
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《小型微型计算机系统》 CSCD 北大核心 2007年第5期940-943,共4页 Journal of Chinese Computer Systems
基金 国家自然科学基金项目(90407002和60576024)资助 上海市科委AM基金项目(0502)资助
关键词 安全Hash算法SHA-1 低成本 VLSI security Hash algorithm low-cost VLSI
分类号 TP309.7 [自动化与计算机技术—计算机系统结构] TN47 [电子电信—微电子学与固体电子学]
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参考文献8

  • 1FIPS PUB 180-1,Secure Hash Standard (SHA-1).National Institute of Standards and Technology (NIST)[S].1995.
  • 2Thull D,Sannino R.Performance considerations for an Embedded Implementation of OMA DRM 2[J].Design Automation and Test in Europe,2005,45-61.
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同被引文献19

  • 1韩军,曾晓洋,陆荣华,赵佳,汤庭鳌.集成模乘求逆双重运算的抗攻击RSA协处理器[J].小型微型计算机系统,2007,28(4):753-758. 被引量：2
  • 2Akyildiz I F, Su W, Sankarasubramaniam Y, et al. Wireless sensor networks: a survey[J]. Computer Networks, 2002, 38(7):393-422.
  • 3Stallings W.密码编码学与网络安全[M].4版.孟庆树,傅建明,译.北京:电子工业出版社,2006.
  • 4National Institute of Standards and Technology. Federal Information Processing Standards (FIPS) Publication 180-1 Secure Hash Standard (SHA-1) [S].Washington: NIST, 1995.
  • 5Michail H, Kakarountas A P, Koufopavlou O. A low-power and high-throughput implementation of the SHA-1 Hash function[C]//IEEE International Symposium on Circuits and Systems. Kobe: IEEE, 2005:4 086-4 089.
  • 6Kaps J P, Sunar B. Energy comparison of AES and SHA-1 for ubiquitous computing[C]//2nd IFIP International Symposium on Network Centric Ubiquitous Systems. Berlin.. Springer, 2006: 372-381.
  • 7Lee Y K, Chan H, Verbauwhede I. Throughput optimized SHA-1 architecture using unfolding transformation[C]//IEEE 17th International Conference on Application-specific Systems, Architectures and Processors. Steamboat Springs, Colorado: IEEE, 2006: 354-359.
  • 8Rabaey J M,Chandrakasan A,Nikolic B.数字集成电路--电路、系统与设计[M].2版.周润德,译.北京:电子工业出版社,2004.
  • 9Stallings W. Cryptography and Network Security: Principles and Practice[M]. 2nd Edition. New Jersey: Prentice Hall, 2002.
  • 10Lu R, Zeng X, Han J. Design and VLSI Implementation of a Security ASIP[C]//7th International Conference on ASIC. Guilin:IEEE Press,2007:866 869.

引证文献2

二级引证文献3

小型微型计算机系统
2007年 第5期

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