一种面向嵌入式SoC设计的混合级硬/软件协同验证技术

A Mixed Level Software and Hardware Co-Verification Solution for Embedded SoC Design

SoC已经成为嵌入式系统必不可少的解决方案。验证如此复杂的嵌入式SoC是非常困难的,系统设计需要新的验证技术更快更好地完成系统功能验证任务。通过比较当前3种主要的嵌入式系统验证技术:软件仿真技术、硬件模拟技术、硬/软件协同验证仿真技术,介绍基于指令集仿真器和FPGA相结合的、面向IP核复用的混合级硬/软件协同验证环境,并提出混合级协同验证总线功能模块的构成。该技术不仅可以提高设计的可信性和验证速度,而且能够继承当前大多数硬件模拟验证方法。

SoC has become an indispensable solution in the embedded systems market. The verification of SoC is so difficult that system design need new solution for fuction verification. This paper focuses on three mainly kinds of verification techniques for embedded system： software simulation, hardware emulation, HW/SW co- verification,and introduces mixed level co - verfication solution based on ISS and FPGAs. Finally it describs the detaily model of bus. The solution not only improves the credibility and speed of verification, but also inherits current most method of hardware emulation.