期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

一种高速TLB的设计与实现

Design and implementation of high-speed TLB
下载PDF
导出
摘要 为了加快微处理器中线性地址向物理地址转换的速度,提出了一种高速TLB结构。结构采用全定制的CAM阵列和SRAM阵列,并根据CAM和SRAM单元的输出特点设计了精巧的读出放大逻辑,有效提高了TLB的读出速度。经流片测试,表明设计正确可靠,能够保证地址转换延时在1ns左右。 A new high-speed TLB architecture is designed for accelerating the address transition rate from linear address to physical one in micro processors.Full custom circuit parts of CAM and SRAM are adopted. According to the output signal characteristic of the tow kinds of storage units ,amplifying and reading circuits are elaborately designed to improve the reading speed of TLB. Taped out chips can work correctly and reliably,and can keep the transition delay at about 1 ns.
作者 刘宗林 吴虎成 唐涛 党桂斌
机构地区 国防科技大学计算机学院
出处 《计算机工程与应用》 CSCD 北大核心 2007年第16期1-3,86,共4页 Computer Engineering and Applications
基金 国家自然科学基金(the National Natural Science Foundation of China under GrantNo.60473079)
关键词 TRANSLATE Look—aside Buffer(TLB) CAM SRAM 替换策略 地址转换 Translate Look-aside Buffer（TLB） CAM SRAM replacement strategy address transition
分类号 TP33 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献5

  • 1范东睿,杨洪波,高光荣,赵荣彩.Evaluation and Choice of Various Branch Predictors for Low-Power Embedded Processor[J].Journal of Computer Science & Technology,2003,18(6):833-838. 被引量：3
  • 2Lee Jung-hoon,Park Oi-ho.A selective filter-bank TLB system[C]//Proceedings of the ISLPED,Seoul Korea,2003:312-317.
  • 3Lee Hsien-Hsin S,Ballapuram Chinnakrishnan S.Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning[C]//Proceedings of the ISLPED,Seoul Korea,2003:306-311.
  • 4Chen J B,Borg A,Jouppi N P.A simulation based study of TLB performance[C]//Proceedings of the International Symposium on Computer Architecture,1992:114-123.
  • 5Min J H,Lee J H,Jeong S W,et al.A selective accessing TLB for high performance and lower power consumption[J].IEEE 2002,2002.

二级参考文献19

  • 1Smith J E. A study of branch prediction strategies. In Proc. the 8th Int. Syrup. Computer Architecture, Minneapolis, 1981, pp.135-148.
  • 2Yeh T Y, Patt Y N. Alternative implementations of two-level adaptive branch prediction. In Proc. the 19th Int. Syrup. Computer Architecture, Queensland, 1992,pp. 124-134.
  • 3Yeh T Y, Patt Y N. Two-level adaptive training branch prediction. In Proc. the 24th Annual Int. Syrup. Microarchitecture, Albuquerque, 1991, pp.51-61.
  • 4Pan S T, So K, Rahmeh J T. Improving the accuracy of dynamic branch prediction using branch correlation.In Proc. the Fifth Int. Conf. Architectural Support for Programming Languages and Operating Systems,Boston, 1992, pp:76-84.
  • 5Chang P Y, Hao E, Patt Y N. Alternative implementations of hybrid branch predictors. In Proc. the 28th Annual Int. Syrup. Microarchitecture, Ann Arbor, 1995,pp.252-257.
  • 6Evers M, Chang PY, Patt Y. Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches. In Proc. 23rd Annual Int. Syrup. Computer Architecture, Philadelphia, 1996,pp.3-11.
  • 7Maria-Dana Tarlescu, Kevin B Theobald, Guang R Gao.Elastic history buffer: A low-cost method to improve branch prediction accuracy. In ICCD'97, Austin, 1997,pp.82-87.
  • 8Kevin B Theobald, Guang R Gao, Laurie J Hendren.Speculative execution and branch prediction on parallel machines. In Proc. 1993 Int. Conf. Supercomputing,Tokyo, 1993, pp.77-86.
  • 9Parikh D, Skadron K, Zhang Y, Barcella M, Stan M.Power issues related to branch prediction. In Proc. the 8th Int. Syrup. High-Performance Computer Architecture, Boston, 2002, pp.233-246.
  • 10Matthew R Guthaus, Jeffrey S Ringenberg, Dan Ernst.MiBench: A free, commercially representative embedded benchmark suite. In IEEE 4th Annual Workshop on Workload Characterization, Austin, 2001, pp.1-12.

共引文献2

计算机工程与应用
2007年 第16期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部