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Yield estimation of metallic layers in integrated circuits 被引量:2

Yield estimation of metallic layers in integrated circuits
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摘要 In the existing models of estimating the yield and critical area, the defect outline is usually assumed to be circular, but the observed real defect outlines are irregular in shape. In this paper, estimation of the yield and critical area is made using the Monte Carlo technique and the relationship between the errors of yield estimated by circular defect and the rectangle degree of the defect is analysed. The rectangular model of a real defect is presented, and the yield model is provided correspondingly. The models take into account an outline similar to that of an original defect, the characteristics of two-dimensional distribution of defects, the feature of a layout routing, and the character of yield estimation. In order to make the models practicable, the critical area computations related to rectangular defect and regular (vertical or horizontal) routing are discussed. The critical areas associated with rectangular defect and non- regular routing are developed also, based on the mathematical morphology. The experimental results show that the new yield model may predict the yield caused by real defects more accurately than the circular model. It is significant that the yield is accurately estimated using the proposed model for IC metals. In the existing models of estimating the yield and critical area, the defect outline is usually assumed to be circular, but the observed real defect outlines are irregular in shape. In this paper, estimation of the yield and critical area is made using the Monte Carlo technique and the relationship between the errors of yield estimated by circular defect and the rectangle degree of the defect is analysed. The rectangular model of a real defect is presented, and the yield model is provided correspondingly. The models take into account an outline similar to that of an original defect, the characteristics of two-dimensional distribution of defects, the feature of a layout routing, and the character of yield estimation. In order to make the models practicable, the critical area computations related to rectangular defect and regular (vertical or horizontal) routing are discussed. The critical areas associated with rectangular defect and non- regular routing are developed also, based on the mathematical morphology. The experimental results show that the new yield model may predict the yield caused by real defects more accurately than the circular model. It is significant that the yield is accurately estimated using the proposed model for IC metals.
出处 《Chinese Physics B》 SCIE EI CAS CSCD 2007年第6期1796-1805,共10页 中国物理B(英文版)
关键词 real defects critical area model mathematical morphology yield estimation real defects, critical area model, mathematical morphology, yield estimation
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参考文献18

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同被引文献27

  • 1王俊平,郝跃.Critical area computation for real defects and arbitrary conductor shapes[J].Chinese Physics B,2006,15(7):1621-1630. 被引量:2
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  • 3田之勤.纳米工艺可制造性设计EDA技术[J].中国集成电路,2007,16(2):30-38. 被引量:1
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