期刊文献+

一种避免内存爆炸的组合电路等价性验证方法

A combinational equivalence checking method avoiding memory explosion
下载PDF
导出
摘要 割集在组合电路等价性验证中得到了广泛的应用,已有的方法常构造能将整个电路一分为二的割集,虽然这种割集在验证后续节点时可以重用已构建的BDD,但它的排序对大多数后续节点都很差,容易引起内存爆炸问题。本文中的割集只针对要验证等价性的某一对点,避免了上述问题。ISCAS85的实验结果表明了它的有效性。 Cut is used wildly in current combinational equivalence checking methods; most of these methods build a cut that can split the original circuit into two small ones. Although this kind of cut can reuse BDDs that already exist, its ordering is so bad for the following nodes and can easily cause memory explosion. The cut in this article only aims at one pair of nodes and can efficiently avoids such explosion. The results based on ISCAS85 show its efficiency.
出处 《电路与系统学报》 CSCD 北大核心 2007年第3期21-25,共5页 Journal of Circuits and Systems
基金 国家自然科学基金资助项目(90207002)
关键词 等价性验证 BDD 割集 equivalence checking BDD cut
  • 相关文献

参考文献9

  • 1Bryant R E.Graph-Based Algorithms for Boolean Function Manipulation[J].IEEE Transactions on Computer,1986,C-35:667-691.
  • 2Huang Shi-Yu,Cheng Kwang-Ting.Formal Equivalence Checking and Design Debugging[M].Kluwer Academic Publishers,1998.
  • 3Fujita M,Fujisawa H,Kawato N.Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams[A].Proceedings of International Conference on Computer-Aided Design[C].1988.2-5.
  • 4Malik S,Wang A,Brayton R,et al.Logic Verification Using Binary Decision Diagrams in a Logic Synthesis Environment[A].Proceedings of International Conference on Computer-Aided Design[C].1998.6-9.
  • 5Rudell R.Dynamic Variable Ordering for Ordered Binary Decision Diagrams[A].Proceeding of International Conference on Computer-Aided Design[C].1993.42-47.
  • 6Berman C L,Trevillyan L H.Functional Comparison of Logic Designs for VLSI Circuits[A].Proceedings of International Conference on Computer-Aided Design[C].1989.456-459.
  • 7Brand D.Verification of Large Synthesized Designs[A].Proceedings of International Conference on Computer-Aided Design[C].1993.534-537.
  • 8Matsunaga Y.An Efficient Equivalence Checker for Combinational Circuits[A].Proceedings of International Conference on Computer-Aided Design[C].1996.629-634.
  • 9Kuehlmann A,Krohm F.Equivalence Checking Using Cuts and Heaps[A].Proceedings of International Conference on Computer-Aided Design[C].1997.263-268.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部