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粗粒度可重构结构的性能估计方法

A method for performance estimation of coarse-grained reconfigurable architecture
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摘要 在设计初期,估计粗粒度可重构结构的性能,对粗粒度可重构结构设计具有指导意义。在考虑局部数据存储器结构以及局部数据存储器与可重构阵列的接口结构的情况下,建立了粗粒度可重构结构的参数模型,使用改进的螺旋形绑定策略将应用算法DFG(Data Flow Graph)中的算子绑定到可重构阵列的处理单元上,提出了一种粗粒度可重构结构的性能估计方法。应用实例表明,在设计初期,该方法能得到周期精确的估计结果,有效地指导粗粒度可重构结构的设计。 In the first step of a design, performance estimation is a guider to developing a coarse-grained reconfigurable architecture. With considering local data memory and interface between local data memory and reconfigurable array, parameter model is established for coarse-grained reconfigurable architecture. Improved spiral binding strategy is applied to bind operators in DFG (Data Flow Graph) of application algorithm to processing elements in reconfigurable array. A new method for performance estimation of coarse-grained reconfigurable architecture is proposed. Experiment results show that it can produce cycle-accurate result and direct the design of coarse-grained reconfigurable architecture effectively at an early stage of design cycle.
出处 《电路与系统学报》 CSCD 北大核心 2007年第3期84-88,共5页 Journal of Circuits and Systems
基金 国家863计划资助课题(2003AA1410502003AA1Z1060)
关键词 粗粒度可重构结构 参数模型 螺旋形绑定策略 局部数据存储器结构 coarse-grained reconfigurable architecture parameter model spiral binding strategy local data memory
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  • 1ROSE A,El GAMAL A,SANGIOVANNI V.Architecture of field programmable gate arrays[J].Proceedings of IEEE,1993,81(7):1013-1029.
  • 2REINER HARTENSTEIN.A Decade of Reconfigurable Computing:a Visionary Retrospective[A].Proceedings of Conference on Design,Automation and Test in Europe[C].2001.642-649.
  • 3GOLDSTEIN S,SCHMIT H,BUDIU M,et al.PipeRench:a reconfigurable architecture and compiler[J].Computer,2000,33(4):70-77.
  • 4MEI B,VERNALDE S,VERKEST D,et al.Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling[A].Proc of Computers and Digital Techniques,IEE Proceedings[C].2003,150(5):255-61.
  • 5HANNIG F,DUTTA H,TEICH J.Regular mapping for coarse-grained reconfigurable architectures[A].Proc of Acoustics,Speech,and Signal[C].2004,5:57-60.
  • 6HARTENSTEIN R,HERZ M,HOFFMANN T,et al.KressArray Xplorer:A New CAD Environment to Optimize Reconfigurable Datapath Array Architectures[A].Proceedings of the ASP-DAC 2000[C].2000.163-168.
  • 7BANSAL N,GUPTA S,PUTT N,et al.Network topology exploration of mesh-based coarse-grain reconfigurable architectures[A].Proceeding of the Design Automation and Test in Europe Conference and Exhibition[C].Austin:IEEE Computer Society,2004.
  • 8HARTEJ SINGH,MING-HAU LEE,GUANGMING LU,et al.Morphosys:an integrated reconfigurable system for data-parallel and computation-intensive applications[J].IEEE Trans on Computers,2000,49(5):465-481.
  • 9LEE J,CHOI K,DUTT N.Compilation approach for coarse-grained reconfigurable architectures[J].Design (Test of Computers,IEEE,2003,20(1):26-33.
  • 10MYAMORI T,OLUKOTUM K.A quantitative analysis of reconfigurable coprocessor for multimedia applications[A].Proc of FPGAs for Custom Computing Machines[C].1998.2-11.

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