一种低存储需求的二维DWT VLSI结构设计方法

A method of VLSI architecture design with low memory requirement for 2-D DWT

为了减少基于提升的二维离散小波变换(DWT)VLSI结构设计中的片内存储需求,采用了一种新颖的调度方法,通过读取少量数据进行行滤波操作,并实现和列滤波的并行处理,有效地减少了片内存储容量。此外,行滤波和列滤波变换内部结构采用流水线设计方法,加快了运算速度,提高了硬件资源利用率,减小了电路的规模,并且这种基于提升的9/7离散小波变换二维结构很方便兼容5/3滤波器。经过Verilog HDL仿真验证,结果表明,在50MHz系统时钟下,采用9/7滤波器经3级分解,每秒钟可处理21帧大小为1280×1024×8bit的灰白图像。

A novel method to schedule the operations involved in the VLSI architecture design for lifting-based 2-D discrete wavelet transforms （DWT） is presented to reduce on-chip memory requirement. By means of processing a few datum with row filter operations that are paralleling with column filter operations, the on-chip memory capacity is progressively reduced. Furthermore, the architecture of the row filter and column filter adoptes a pipelined method that speeded up the transforms and improves the hardware utilization. The whole architecture for 9/7 2-D DWT can also be easily compatible with 5/3 filter. The simulation results which are simulated through Verilog HDL indicate that this design using 9/7 filter with 3 level decompositions is able to perform compression of 1280×1024×8bit grayscale images with the speed of 21 frames per second （fps） at 50MHz system clock.