SEC中的全数字锁相环的分析及设计

Analysis and design of all digital phase-locked loops in SEC

文章首先介绍了全数字锁相环(ADPLL)的基本结构和工作原理,并进行了数学建模,计算了其主要的参数指标;然后,针对SDH设备时钟(SEC)设计了一种切实可行的低抖动ADPLL的电路结构,并对其各个组成部分进行了具体的电路分析和设计,通过微机适当配置,可以使该设计的结果得到优化;最后,通过现场可编程门阵列(FPGA)验证,给出了测试结果。

In this paper, the basic structure and operating principle of ADPLL （All Digital Phase -Locked Loop） are first introduced, which is followed by the analyses of its mathematic model and the calculation of its main parameters. Then, a feasible low-jltter ADPLL circuit structure for SEC（SDH equipment clock） is designed and specific circuit analysis of and designs for each part of ADPLL made, which is optimized by appropriate CPU configurations. Finally, this circuit is verified by FPGA and the test result given.