一种深度流水线的浮点加法器

Deeply Pipelining Floating-Point Adder

随着数字信号处理技术的发展,FPGA正越来越频繁地用于实现基于高速硬件的高性能的科学计算.本文通过增加浮点加法器的流水线级数来提高其单位时间的吞吐量,探讨了充分利用FPGA内部丰富的触发器来提高系统主频的可行性.提出了一种指数和尾数操作、加法和减法操作均分离的多路径浮点加法器结构,对于单精度(32位)的操作数,采用Altera公司的StratixⅡ系列芯片,8级流水线可以达到356MHz以上的速度.

FPGAs are increasingly being used in the high performance and scientific computing community to implement floating-point based hardware accelerators. The throughput was improved by increasing the number of pipelining stages of floating-point adder, and the feasibility of advancing the system clock rate was researched by making the most of plenty of flip-flops in FPGA. The multi-paths floating-point adder/subtractor architecture which both index operation and mantissa operation, addition and subtraction were separated apart was presented. For single precision （32 bits） operation, we used Altera＇s StratixⅡ family chip, achieved throughput rates more than 356 MHz by eight-stage deeply pipeliniug.