可制造性设计在纳米SOC中的应用和发展

Applications and Trends of DFM Technology for Nanoscale SOC

随着图形特征尺寸的不断缩小、集成度的不断提高,集成电路已进入纳米系统芯片(SOC)阶段,摩尔定律依靠器件尺寸缩小得以延续的方式正面临着众多挑战。分析了纳米SOC中影响性能和良品率的关键效应及相应的措施。从半导体产业链的发展演变指出了可制造性设计(DFM)是纳米SOC阶段提高可制造性与良品率的解决方案。与光刻性能相关的分辨率增强技术(RET)是推动DFM发展的第一波浪潮,下一代的DFM将更注重良品率的受限分析及设计规则的综合优化。综述了DFM产生的历史及发展的现状,并对其前景进行了展望。

With the continuous scaling down of feature dimension, IC industry has entered the era of nano-SOC. Moore＇s Law, which depends on the scaling down of device dimension, is facing many challenges. The key effects are analyzed, which influence the performance and yield of nano-SOC. The corresponding measures are also explained. It can be concluded from the development and change of semiconductor industry chain that the design for manufacturability （DFM） can improve the manufacturability and yield in nano-SOC era. The resolution enhancement techniques （RET） relating lithography performance drove the foremost development of DFM. The next generation DFM will pay more attention to yield, rule synthesis and optimization. The history and status of DFM are presented, and the future of it is also prospected .