高压CMOS电路的设计及制造工艺研究

A Technology of Layout Design and Process for High Voltage CMOS Circuit Compatible with General Circuit

介绍了一种与常规CMOS电路兼容的高压CMOS电路版图设计及工艺加工技术。在该技术中采用了非自对准的场区掺杂,增加场区掺杂浓度,轻掺杂漏区以形成漂移区等提高MOS晶体管击穿电压的一系列技术措施,使MOS晶体管的源漏击穿电压提高至35V以上,电路在24V电压下可以正常工作。

A technology of layout design and process for high voltage CMOS circuit compatible with general CMOS circuit is designed. Non - self - alignment field doping is used to increase the doping density of the field region and the light - doping of drain - region makes drift region to raise MOS transistors＇ breakdown voltage. The MOS transistors＇ source - drain breakdown voltage can be over 35V. The circuit can work normally under the voltage of 24V.