改进BM算法的高速RS译码器方案及其FPGA实现

A High-Speed RS Decoder Using Extended BM Algorithm Based on FPGA

介绍了一种高速的RS译码器的结构方案。由于一般BM算法的实现结构不规则,以及延时过长的缘故,在VLSI的设计中,广泛采用的是eE算法,采用的改进BM算法,使得BM算法的实现结构规则,并且延时更小。另外还采用了一种新的有限域乘法结构,有规则的结构,易于HDL语言实现。

A high-speed RS（Reed-Solomon） decoder architecture is presented. BM algorithm is irregular and has a longer critical path delay which is dependent on the error-correcting capability of the code. An architecture based on the eE（extended Euclidean） algorithm is used in the majority of the implementations for the sake of the irregular architectures in BM algorithm. An architecture based on a modified BM algorithm is regular and has less critical path delay. Finally, a new GF multiplied architecture is adopted for regular architecture.