一种高速CMOS预放大锁存比较器

A high-speed CMOS preamplifier-latch comparator

介绍了一种适合于高速模数转换器(ADCs)的预放大-锁存(preamplifier-latch)CMOS比较器。此电路结构包括一个预放大器、锁存比较器和输出缓冲器。在预放大器和正反馈锁存比较器之间加入分离电路,以此来减少回扫(kickback)噪声对电路的影响。采用0.35μm标准CMOS工艺库,在Cadence环境下进行仿真,该比较器在时钟频率为500 MHz,采样频率为40 MHz的时候,可以达到30μV的精度,功耗大约为0.6 mW。

A preamplifier-latch CMOS comparator especially for high-speed ADCs is described in this paper. It consists of a preamplifier, a latch stage and output buffer. The proposed comparator separates preamplifier from the positive feedback latched comparator so as to reduce the influence of the kickback noise. Simulation results based on standard CMOS 0.35μm technology show that, this comparator can achieve 30 μV sensitivity while only 0.6 mW power dissipation at 40 MHz.