基于Virtex-4 FPGA的低功耗图像融合系统

Low power image fusion system based on Virtex-4 FPGA

基于电源模块、外部存储器和FPGA器件等具体分析了融合系统的低功耗设计。FPGA器件选择了Xilinx公司针对高性能信号处理的Virtex-4 SX35三百万门级芯片,电源模块采用TI公司的两片TPS54310和一片TPS54610,具有低功耗特性,电压调节范围为0.9～3.3 V,调节精度可达1%。外部存储器使用高速、低功耗的ZBT SRAM存储器,消除了标准SRAM器件存在的读和写周期间的等待状态和空闲周期,该功能可极大地改善存储器性能,在存在频繁的读/写操作变换时效果更佳。结合图像融合算法的特点和Virtex-4 SX系列FPGA的资源与技术优势,讨论了在总线编码、流水线设计和并行处理等方面的低功耗设计方法。结果显示:采用此技术设计的融合系统有效降低了系统的实际功耗,其动态功耗降幅可达50%,为提高融合系统的可靠性提供了有力支持。

In order to reduce the power consumption of image fusion system based on FPGA, the main factors impacting on the system power consumption were introduced. Then the low power designs of main modules in the system were analyzed in detail, including power module, outer memorizer, FPGA device and so on. The Virtex-4 SX35 FPGA equaling to a device of three million logic gates produced by Xilinx for high-performance signal processing was selected, and TPS54310 and TPS54610 with low power character,and adjustable output voltage of 0. 9～3. 3 V and accuracy of 1% designed by TI were used to produce the main system power. ZBT SRAM was chosen for outer memorizer to realize unlimited true back-to-back read/write operations without waiting states, it can dramatically improve the throughput of data in system, especially when it requires write/read transitions frequently. With the characteristics of fusion algorithms and the advantages in resource and technology of Virtex-4 FPGAs, the particular low power design was discussed around such techniques as bus coding, pipeline design and parallel processing, etc. The analytic conclusions indicate that the real power consumption of the system can be reduced effectively and its reliability can be guaranteed if the foregoing designs are adopted properly.