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基于MSP430F149的频率计设计

Design of MSP430F149-Based Frequency Counter
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摘要 设计了一种以超低功耗单片机MSP430F149为控制器,以高速的CPLD(复杂可编程逻辑器件)实现32位计数的频率计。在设计中应用单片机的数学运算和控制功能,实现了测量时间闸门的自动选择,频率和周期的统一处理。此外,利用MSP430F149内部的高速模拟比较器,实现了对正弦波小信号的预处理,使得该频率计能够在较宽的频率范围和幅度范围内进行测量。 A frequency counter is designed, in which an ultra-low-power microcontroller MSP430F149 is used as a controller and a high speed CPLD (complex programmable logic device) is used as a 32-bits counter. In the design the time gate can be selected automatically and both cycle and frequency can be measured by making use of the operation and control functions of microcontroller. In addition, the high-speed on-chip comparator of MSP430F149, being used to pre-treat the small sine wave signal, enable the frequency counter to measure signals at a wide range of frequency and voltage.
出处 《时间频率学报》 CSCD 2006年第2期116-122,共7页 Journal of Time and Frequency
关键词 MSP4 30F149单片机 复杂可编程逻辑器件(CPLD) 频率计 rnicrocontroller MSP430F149 CPLD(complex programmable logic device) frequency counter
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参考文献1

  • 1Kay S. Statistically/computationally efficient frequency estimation[A]. Proceedings of IEEE international conference in acoustic speech and signal processing[C]. New York: IEEE service center, 1988.2292-2295.

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