全定制单元时序模型的建立

Setup of Full-custom cell Timing Model

随着集成电路规模的不断增大,工艺尺寸的不断缩小,各种短沟效应及互连效应对电路性能的影响日益加重,时序收敛成为设计者面临的最棘手问题之一。时序验证是对电路的时序特性进行分析,检查设计能否满足性能要求,它在验证工作中占有非常重要的地位,是辅助设计人员寻找电路性能瓶颈的最主要手段。针对静态时序分析(STA)的应用,本文提出了为全定制单元建立时序模型的方法。这个方法考虑了信号渡越时间和输出负载的影响,经实验证明这个方法是可行的。

As the design size keeps growing and the feature size keeps scaling down in integrated circuits, the effects of short channel and interconnector are major factors in determining the performance, so that timing convergence has become one of the most intractable problem for designers. According to the application of STA, this paper presented a method to setup the timing model of full-custom cell. It contains the effects of signal slew and load of output pin, which was proved to be effectible by experiment.