一种多位计数器的设计方法

Method for Designing Multi-bit Counter

本文提出了一种设计多位计数器的方法,以及该方法的相关原理和算法。该方法先把多位计数器拆分成多个较小计数器,从而构造出多周期路径,然后通过施加多周期路径约束实现高性能的多位计数器,其本质是逻辑平衡思想的衍生。采用该法设计的多位计数器比采用传统方法设计的计数器,在频率、面积、功耗这三个性能指标上都有明显的改善。

This paper proposes a method for designing multi-bit counter and introduces its principle and related arithmetic. According to the method, it is necessary to built multi-cycle paths by splitting one multi-bit counter into two or more counters related each other firstly. Then, multi-cycle path constraints are added on the paths to implement the multi-bit counter. The essence of the method is the concept of logic balance, in other words, it is logic balance enhanced between one cycle and multi-cycles. In order to validate the feasibility of the method, we implemented a 32bit counter that is a firm core according to the method. Compared with the counter implemented using traditional method, we have found that it has better performances in frequency, total cell area and power consumption. Besides, this method is also useful for designing other similar circuits and EDA tools.