基于FPGA技术的高速信道编解码芯片的优化设计

Optimized Design of High-Speed Channel Coding and Decoding Chip Based on FPGA

综述了目前国内外运用现场可编程门阵列(Field Programmable Gate Array,FPGA)进行数字电视高速信道编解码芯片开发的技术现状和发展动向。对技术“瓶颈”进行了分析,依据RS码(Reed-Solomon code)、卷积(Coil Accumulation,CA)编码和Viterbi编码和FPGA开发等技术,设计开发了一种具备自主知识产权的数字电视高速信道编解码芯片。它属于一种全新功能的应用级数字编解码产品,既可作为单元电路应用于数字电视系统,也可为实现数字电视高速信号处理的片上集成系统(System on Chip,SOC)设计提供模块电路。

The paper analyzes the status quo and developing trend of high-speed channel coding and decoding chip for digital television. Based on RS Coding and Decoding, Coiling Integral Coding, Viterbi Coding and FPGA, an authorized high-speed channel coding and decoding chip for digital television is designed and developed, which is a new digital coding product for practice application. It can be applied into digital television system as part of cell circuit. It also can be provided as basic IC in SOC designing for high speed digital signal＇s disposing of digital televison.