基于FPGA的Turbo译码交织器设计

Design of Turbo Decoder Interleaver Based on FPGA

介绍了一种Turbo译码交织器的现场可编程门阵列(Field Programmable Gate Array,FPGA)硬件实现方案,将交织算法的软件编程和FPGA内部的硬件存储块相结合,有效地降低了译码器的硬件实现复杂度,减小了译码延时,并且给出了具体的译码器内交织器FPGA实现原理框图。

This paper has introduced a FPGA implementation scheme of interleaver of turbo decoder. This scheme, which combines software programme of interleaver algorithm with the block memory of FPGA, effectively reduces the implementation complexity of the decoder, and the delay of decoding, and shows a detailed FPGA implementation schematic diagram.